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MSE Seminar - Prof. Deep Jariwala (11 March 2025)
11 Mar 2025 (Tue) | 10:30 AM - 11:30 AM

250311_MSE Seminar_Prof. Deep Jariwala

MSE Seminar – Prof. Deep Jariwala (11 March 2025)

Title: 2D Materials for Next-Generation Electronics: From Low-Power Logic to Monolithic Memory
Speaker: Prof. Deep Jariwala
University of Pennsylvania, USA
Date: 11 March 2025 (Tuesday)
Time: 10:30 – 11:30 am
Venue: B5-210, Yeung Kin Man Academic Building
Abstract:

Silicon has been the dominant material for electronic computing for decades and very likely will stay dominant for the foreseeable future. However, it is well-known that Moore's law that propelled Silicon into this dominant position is long dead. Therefore, a fervent search for (i) new semiconductors that could directly replace silicon or (ii) new architectures with novel materials/devices added onto silicon or (iii) new physics/state-variables or a combination of above has been the subject of much of the electronic materials and devices research of the past 2 decades. The above problem is further complicated by the changing paradigm of computing from arithmetic centric to data centric in the age of billions of internet-connected devices and artificial intelligence as well as the ubiquity of computing in ever more challenging environments. Therefore, there is a pressing need for complementing and supplementing Silicon to operate with greater efficiency, speed and handle greater amounts of data. This is further necessary since a completely novel and paradigm changing computing platform (e.g. all optical computing or quantum computing) remains out of reach for now.

The above is however not possible without fundamental innovation in new electronic materials and devices. Therefore, in this talk, I will try to make the case of how novel layered two-dimensional (2D) chalcogenide materials and three-dimensional (3D) nitride materials might present interesting avenues to overcome some of the limitations being faced by Silicon hardware. I will start by presenting our ongoing and recent work on integration of 2D chalcogenide semiconductors with silicon to realize low-power tunnelling field effect transistors. In particular I will focus on In-Se based 2D semiconductors for this application and extend discussion on them to phase-pure, epitaxial thin-film growth over wafer scales, at temperatures low-enough to be compatible with back end of line (BEOL) processing in Silicon fabs.

I will then switch gears to discuss memory devices from 2D materials when integrated with emerging wurtzite structure ferroelectric nitride materials namely aluminium scandium nitride (AISCN). First, I will present on Ferroelectric Field Effect Transistors (FE-FETs) made from 2D materials when integrated with AlScN and make the case for 2D semiconductors in this application. Finally, I will end with showing our most recent results on scaling 2D/AIScN FE-FETs, achieving ultra-high carrier and current densities in ferroelectrically gated MoS2, and also demonstrate negative-capacitance FETs by engineering the AIScN/dielectric/2D interface.

Enquiries: [email protected]
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